In recent years, a cluster system to realize high availability and scalability has been introduced in preparation against a fault etc. of an information processing apparatus. The cluster system connotes a system operated as one single system on the whole by connecting a plurality of information processing apparatuses. This architecture enables the cluster system to distribute a load through the plurality of information processing apparatuses. Further, the cluster system enables, even if one information processing apparatus stops executing a process due to a fault, another information processing apparatus to continue the process. Moreover, the cluster system enables, when used as a server, the load to be distributed via the plurality of information processing apparatuses. The information processing apparatuses connected in the cluster system are called nodes. Each node includes a CPU (Central Processing Unit) serving as an arithmetic processing device and a memory serving as a main storage device. In the cluster system where communications are performed between the plural nodes, the CPU of a certain node may consume a futile amount of electric power while performing the communication for acquiring data on the memory of another node as the case may be. A period of communication time elongates in comparison to a period of arithmetic time of the CPU due to an enlargement in scale of the cluster system. Therefore, the CPU has a tendency to consume the electric power with futility.
A distributed shared memory system is given as one of methods for enabling the cluster system. In the distributed shared memory system, the plurality of nodes is connected via a network used for transferring data, etc. The network establishing connections between the plurality of nodes is called an “interconnect”. The distributed shared memory system virtualizes the plurality of information processing apparatuses connected via the high-speed interconnect into one single information processing apparatus. Therefore, the distributed shared memory system can execute in parallel a multiplicity of threads each defined as an execution unit of a program. Furthermore, the distributed shared memory system shares memories being possessed by the respective nodes with the whole system and enables the memories to be accessed mutually from the CPUs of the individual nodes, thereby having an advantage that a large capacity memory can be utilized.
Herein, a process executed by the CPU of a certain node makes use of the memory as one memory space called a virtual address space. The virtual address space is managed in a unit called a page, and the process accesses a certain page and thus acquires data used for executing a program. At this time, such a case occurs that a physical memory which stores actual data of the page to be accessed by the node is not allocated to a local memory defined as the memory within the self-node. If the page to be accessed is not allocated to the local memory, an exception called a page fault occurs. When the page fault occurs, the CPU executes a process of acquiring the page to be accessed through a process called an exception process or an interrupt process. The information processing apparatus, if configured as a single apparatus, executes a process such as acquiring the page saved in a secondary storage device like an HDD etc. into the local memory. On the other hand, in a distributed shared memory system, a case exists, in which a page saved in the secondary storage device like the HDD etc. exists in a memory of another node, and data of this page are acquired from the another node. In order to acquire the data of the page from a remote memory defined as a memory of another node, a communication process occurs. During this communication process, the CPU expends some time for waiting till the communication will have been completed and, nevertheless, consumes futile electric power for operating at a high CPU clock frequency.
The power consumption of the CPU is proportional to a product of a square of a voltage and the clock frequency and can be therefore reduced by setting low the voltage and the clock frequency of the CPU. A DVFS (Dynamic Voltage and Frequency Scaling) mechanism is known as a technology for controlling the voltage and the clock frequency of the CPU. The CPU equipped with this DVFS mechanism may vary the voltage and the clock frequency. The clock frequency of the CPU will hereinafter be referred to as the CPU clock frequency.    [Patent document 1] Japanese Laid-Open Patent Publication No.S61-49268    [Patent document 2] Japanese Laid-Open Patent Publication No.2005-182103    [Patent document 3] Japanese Laid-Open Patent Publication No.2003-323334    [Non-Patent document 1] Venkatesh Pallipadi, Alexey Starikovskiy, “The Ondemand Governor”, Canada, Proceedings of the Linux Symposium, July 19th-22nd, 2006, Volume Two    [Non-Patent document 2] Nakashima Kouta, Sato Mitsuru, Kumon Kouichi and Taniguchi Hideo, “Design and Evaluation of a Virtual Machine Migration using RDMA Data Transfer Mechanism over 10 Gb Ethernet”, Research Journal of Information Processing Association of Japan, Computing System 48(SIG_18 (ACS_20)), 2007-12-15, p.69-82    [Non-Patent document 3] “Enhanced Intel(R) SpeedStep(R) Technology for the Intel (R) Pentium (R) M Processor”, March 2004    [Non-Patent document 4] Bhavyasree Unni, Nazia Parveen, Ankit Kumar, B. S. Bindhumadhava, “An intelligent energy optimization approach for MPI based applications in HPC systems”, CSI Publications 2013, p.2    [Non-Patent document 5] Konstantinos Koukos, David Black-Schaffer, Vasileios Spiliopoulos, Stefanos Kaxiras, “Towards More Efficient Execution: A Decoupled Access-Execute Approach”, ICS'13, 2013, Uppsala University